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ML12561
Crystal Oscillator
Legacy Device: Motorola MC12561
The ML12561 is the military temperature version of the commercial ML12061 device. It is for use with an external crystal to form a crystal controlled oscillator. In addition to the fundamental series mode crystal, two bypass capacitors are required (plus usual power supply pin bypass capacitors). Translators are provided internally for MECL and TTL outputs. * * * * Frequency Range = 2.0 to 20 MHz Operating Temperature Range TA = -55 to +125C Single Supply Operation: +5.0 Vdc or -5.2 V DC Three Outputs Available: 1.Complementary Sine Wave (600 mVpp typ) 2.Complementary MECL 3.Single Ended TTL
Figure 1. Block Diagram
Bias Bypass 0.1 F 7 VCC AGC Filter 0.1 F 1 VCC 4 Sine Wave Output - 3 2 + 14 - 15 + 16 VCC 13 12 11 VCC
16 1
CERDIP 16 = E CERAMIC PACKAGE CASE 620
MECL Output
CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE CERDIP 16 12561/BEA ML12561/BEA
Voltage Reg.
Crystal Osc. AGC
Ampl./ AGC
Sine to MECL
MECL to TTL Translator
10 TTL Output
6
5 Crystal
8
VEE
9
VEE
Note: 0.1 F power supply pin bypass capacitors not shown.
/ML12561
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ML12561
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 1 1 11 16 Input Current IinH IinL Differential Offset Voltage Output Voltage Level Logic `1' Output Voltage V Vout VOH1 (Note 1) VOH2 Logic `0' Output Voltage VOL1 (Note 1) VOL2 Logic `1' Threshold Voltage Logic `0' Threshold Voltage Output Short Circuit Current
NOTE:
0C Min - - - - - - - - - - - - 4.0 4.0 2.4 2.98 2.98 - - 3.98 3.98 - - 20 Max - - - - - - - - - - - - 4.16 4.16 - 3.43 3.43 0.5 0.5 - - 3.45 3.45 60 Min 13 18 - 13 - - - - 40 -200 - - 4.04 4.04 2.4 3.0 3.0 - - 4.02 4.02 - - 20
+25C Typ 16 23 3.0 16 - - - - - 0 3.5 3.5 - - - - - - - - - - - - Max 19 28 4.0 19 250 250 1.0 1.0 325 +200 - - 4.19 4.19 - 3.44 3.44 0.5 0.5 - - 3.46 3.46 60 Min - - - - - - - - - - - - 4.1 4.1 2.4 3.02 3.02 - - 4.08 4.08 - - 20
+75C Max - - - - - - - - - - - - 4.28 4.28 - 3.47 3.47 0.5 0.5 - - 3.49 3.49 60 Vdc Vdc mAdc Vdc Adc Adc mAdc Vdc Vdc Unit mAdc
Characteristic Power Supply Drain Current
Symbol ICC
14 15 14 15 4 to 7 2 to 3 2 3 12 13 10 12 13 10 10 12 13 12 13 10
VOHA VOLA IOS
1. Devices will meet standard MECL logic levels using VEE = -5.2 Vdc and VCC = 0.
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ML12561
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature 0C +25C +75C Pin Under Test 1 1 11 16 Input Current IinH IinL Differential Offset Voltage Output Voltage Level Logic `1' Output Voltage V Vout VOH1 (Note 1) VOH2 Logic `0' Output Voltage VOL1 (Note 1) VOL2 Logic `1' Threshold Voltage Logic `0' Threshold Voltage Output Short Circuit Current
NOTE:
VIHmax 4.16 4.19 4.28
VILmin 3.19 3.21 3.23
VIHAmin 3.86 3.90 3.96
VILAmax 3.51 3.52 3.55
VIHT 4.0 4.0 4.0
VCCL 4.75 4.75 4.75
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax - - 14 - 14 15 15 14 - - - - 14 15 15 15 14 14 14 - - - - 15 VILmin - - 15 - 15 14 - - - - - - 15 14 14 14 15 15 15 - - - - 14 VIHAmin - - - - - - - - - - - - - - - - - - - 14 15 15 14 - VILAmax - - - - - - - - - - - - - - - - - - - 15 14 14 15 - VIHT - - - - - - - - 5,6 4 4 4 - - - - - - - - - - - - VCCL - - - - - - - - - - - - - - 11,16 - - 11,16 - - - - - 11,16 Gnd 8 8 8,9 8 8 8 8,14 8,15 8 - 8 8 8 8 8,9 8 8 8,9 8,9 8 8 8 8 8,9,10
Characteristic Power Supply Drain Current
Symbol ICC
14 15 14 15 4 to 7 2 to 3 2 3 12 13 10 12 13 10 10 12 13 12 13 10
VOHA VOLA IOS
1. Devices will meet standard MECL logic levels using VEE = -5.2 Vdc and VCC = 0.
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ML12561
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature 0C +25C +75C Pin Under Test 1 1 11 16 Input Current IinH IinL Differential Offset Voltage Output Voltage Level Logic `1' Output Voltage V Vout VOH1 (Note 1) VOH2 Logic `0' Output Voltage VOL1 (Note 1) VOL2 Logic `1' Threshold Voltage Logic `0' Threshold Voltage Output Short Circuit Current
NOTE:
mA VCCH 5.25 5.25 5.25 IOL 16 16 16 IOH -0.4 -0.4 -0.4 IIL -2.5 -2.5 -2.5
VCC 5.0 5.0 5.0
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VCC 1 1 11,16 16 16 16 16 16 1 - 1 1 16 16 - 16 16 - - 16 16 16 16 - VCCH - - - - - - - - - - - - - - - - - - 11,16 - - - - - IOL - - - - - - - - - - - - - - - - - 10 10 - - - - - IOH - - - - - - - - - - - - - - 10 - - - - - - - - - IIL - - - - - - - - - - - - 12 13 - 12 13 - - 12 13 12 13 - Gnd 8 8 8,9 8 8 8 8,14 8,15 8 - 8 8 8 8 8,9 8 8 8,9 8,9 8 8 8 8 8,9,10
Characteristic Power Supply Drain Current
Symbol ICC
14 15 14 15 4 to 7 2 to 3 2 3 12 13 10 12 13 10 10 12 13 12 13 10
VOHA VOLA IOS
1. Devices will meet standard MECL logic levels using VEE = -5.2 Vdc and VCC = 0.
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ML12561
LANSDALE Semiconductor, Inc.
Figure 6. AC Characteristics - MECL and TTL Outputs
t+ 20% 80% 50% t+ + 50% TTL Output (Pin 10) MECL Output (Pin 13) MECL Output (Pin 12) t++ 50% 20% t+- 80% t+ t- + 50% 20% t- All input and output cables to the scope are equal lengths of 50 coaxial cable. Unused outputs are connected to a 50 1% resistor to ground. t+ 80% t- 8 0.1 F 9 CT 400 MMD6150 or Equiv MMD7000 or Equiv VEE = - 3.0 Vdc - 3.0 Vdc + 2.0 Vdc t- -
Pulse Generator (EH 137 or Equiv) PRF = 2.0 MHz t + = t - = 2.0 0.2 ns
t-
+200 mV -200 mV t- - 15 0.1 F 16
VCC = + 2.0 Vdc
Input (Pin 15)
11
13
450
12 10
450 1.2 k
14
C T = 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance.
Test Limits
TEST VOLTAGES/WAVEFORMS APPLIED TO PINS LISTED BELOW:
Characteristic Propagation Delay
Symbol t15 + 10 + t15 - 10 - t15 + 12 - t15 - 12 + t15 + 13 + t15 - 13 - t12 + t13 + t12 - t13 -
Pin 0C + 25C + 75C Under Test Min Max Min Typ Max Min Max Unit Pulse In Pulse Out + 2.0 Vdc - 3.0 Vdc Gnd 10 10 12 12 13 13 12 13 12 13 -- -- -- -- -- -- -- -- -- -- 22 19 5.2 5.0 4.8 5.0 4.0 4.0 4.0 4.0 -- -- -- -- -- -- -- -- -- -- 17 12 4.3 3.7 4.0 4.0 3.0 3.0 3.0 3.0 25 18 5.5 5.2 5.0 5.0 4.0 4.0 4.0 4.0 -- -- -- -- -- -- -- -- -- -- 27 18 5.8 5.2 5.2 5.1 4.4 4.4 4.0 4.0 ns 15 10 10 12 12 13 13 12 13 12 13 11,16 8,9 14
Rise Time Fall Time
ns ns ns ns
15 15 15 15
11,16 11,16 11,16 11,16
8,9 8,9 8,9 8,9
14 14 14 14
Characteristic Sine Wave Amplitude
Pin Under Test 2 3
+ 25C Min 650 650 Typ 750 750 Unit mVp-p
TEST VOLTAGE APPLIED TO PINS LISTED BELOW + 2.0 Vdc 1 - 3.0 Vdc 8,9
Figure 7. AC Test Circuit - Sine Wave Output
All output cables to the scope are equal lengths of 50 coaxial cable. All unused cables must be terminated with a 50 1% resistor to ground. 450 resistor and the scope termination impedance constitute a 10:1 attenuator probe. Crystal -- Reeves Hoffman Series Mode, Series Resistance Minimum at Fundamental f = 10 MHz RE = 5 *RS = 15 k is inserted only for test purposes. When used with the above specified crystal, it guarantees oscillation with any crystal which has an equivalent series resistance 155 Rp: will improve start up problems value: 200-500
VCC = + 2.0 Vdc 0.1 F 1 0.1 F
0.1 F 4 3 2 450 450
6
5 *RS Rp
8
9 VEE = - 3.0 Vdc 0.1 F
Crystal
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ML12561
LANSDALE Semiconductor, Inc.
f, FREQUENCY SHIFT (ppm)
The ML12561 consists of three basic sections: an oscillator with AGC and two translators. Buffered complementary sine wave outputs are available from the oscillator section. The translators convert these sine wave outputs to levels compatible with MECL and/or TTL. Series mode crystals should be used with the oscillator. If it is necessary or desirable to adjust the crystal frequency, a reactive element can be inserted in series with the crystal -- an inductor to lower the frequency or a capacitor to raise it. When such an adjustment is necessary, it is recommended that the crystal be specified slightly lower in frequency and a series trimmer capacitor be added to bring the oscillator back on frequency. As the oscillator frequency is changed from the natural resonance of the crystal, more and more dependence is placed on the external reactance, and temperature drift of the trimming components then affects overall oscillator performance. The ML12561 is designed to operate from a single supply -- either +5.0 Vdc or -5.2 Vdc. Although each translator has separate VCC and VEE supply pins, the circuit is NOT designed to operate from both voltage levels at the same time. The separate VEE pin from the TTL translator helps minimize transient disturbance. If neither translator is being used, all unused pins (9 thru 16) should be connected to VEE (pin 8). With the translators not powered, supply current drain is typically reduced from 42 mA to 23 mA for the ML12061. Frequency Stability Output frequency of different oscillator circuits (of a given device type number) will vary somewhat when used with a given test setup. However, the variation should be within approximately 0.001% from unit to unit. Frequency variations with temperature (independent of the crystal, which is held at 25C) are small -- about -0.08ppm/C for ML12061 operating at 8.0 MHz. Signal Characteristics The sine wave outputs at either pin 2 or pin 3 will typically range from 800 mVp-p (no load) to 500 mVp-p (120 ohm AC load). Approximately 500 mVp-p can be provided across 50 ohms by slightly increasing the DC current in the output buffer by the addition of an external resistor (680 ohms) from pin 2 or 3 to ground, as shown in Figure 9. Frequency drift is typically less than 0.0003% when going from a high-impedance load (1 megohm, 15pF) to the 50 ohm load of Figure 9. The DC voltage level at pin 2 or 3 is nominally 3.5 Vdc with VCC = +5.0 Vdc. Harmonic distortion content in the sine wave outputs is crystal as well as circuit dependent. The largest harmonic (third) will usually be at least 15 dB down from the fundamental. The harmonic content is approximately load independent except
that the higher harmonic levels (greater than the fifth) are increased when the MECL translator is being driven. Typically, the MECL outputs (pins 12 and 13) will drive up to five gates and the TTL output (pin10) will drive up to ten gates. Noise Characteristics Noise level evaluation of the sine wave outputs operation at or 9.0 MHz, indicates the following characteristics: 1. Noise floor (200 kHz from oscillator center frequency) is approximately -122 dB when referenced to a 1.0 Hz bandwidth. Noise floor is not sensitive to load conditions and/or translator operation. 2. Close-in noise (100 Hz from oscillator center frequency) is approximately -88 dB when referenced to a 1.0 Hz bandwidth.
Figure 8. Frequency Variation Due to Temperature
+10 VCC = +5.0 Vdc Tcrystal = 25C 0 ML12561 -10
-20 ML12561 -30 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE () 100 125
Figure 9. Driving Low Impedance Loads
+5.0 V 0.1 F 0.1 F
0.1 F 7 1 4 2 or 3 0.1 F
6
5
8
680
50
* See text under signal characteristics.
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ML12561
LANSDALE Semiconductor, Inc.
Figure 10. MECL Translator Load Capability
VCC = +5.0 V
Figure 11. TTL Translator Load Capability
VCC = +5.0 V 0.1 F 11 Sine to MECL 13 12 15 pF 8 8.2 k 9 MECL to TTL Translator 0.1 F
+5.0 V
16
270
10 15 pF 1.5 k All diodes MBD101 or Equiv
Figure 12. Noise Measurement Test Circuit
+5.0 V 0.1 F 0.1 F
ANALYZER SETTING Measurement Sweep 50 kHz/div 20 kHz/div Bandwidth 10 kHz 10 Hz Video Filter 10 Hz 10 Hz
0.1 F 7 1 4 2 or 3 0.1 F To HP8552B/53B Spectrum Analyzer or Equiv
Noise Floor Close-In Noise
6
5
8
750
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ML12561
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RESISTOR R3 (2 Places) ML12061 400 2 k 200 R2 (2 Places) R1 (2 Places)
Oscillator Sine to MECL Translator Amplifier / AGC MECL to TTL Translator 16 VCC 2.98k 241 241 15+ 14- 12 MECL Output 13 1.2k 11 VCC VCC 1 410 AGC Filter 4 Sine Wave Output 23 + -
Voltage Regulator
Bias 7
Figure 13. Circuit Schematic
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R1 R1 410 R2 Crystal 6 5 8 R3 R3 R2 9.32k VEE 205 1.5k 1.5k 58 2 1.4k 130
1k
260
100
10 680 54 0 TTL Output
500
750
4 10
9.32k
20
20 VEE 9
LANSDALE Semiconductor, Inc.
Issue 0
ML12561
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
CERDIP 16 = E CERAMIC PACKAGE (ML12561/BEA) CASE 620 ISSUE R
9
-A-
16
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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